Memory devices are structured to have one or more arrays of memory cells that are arranged in rows and columns. Each memory cell stores data as an electrical charge that is accessed by a digit line associated with the memory cell. A charged memory cell, when the memory cell is selected, causes a positive change in voltage on the associated digit line, and a selected memory cell that is not charged causes a negative change in voltage on the associated digit line. The change in voltage on the digit line may be amplified and detected by a sense amplifier to indicate the value of the data bit stored in the memory cell.
Conventional sense amplifiers are typically coupled to a pair of complementary digit lines to which a large number of memory cells (not shown) are connected. Sense amplifiers typically improve the accuracy of determining the state of the selected memory cells. As known in the art, when memory cells are accessed, a row of memory cells are activated and sense amplifiers are used to amplify cell data for the respective column of activated memory cells by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have complementary logic levels. Each sense amplifier typically includes a pair of cross-coupled NMOS transistors and a pair of cross-coupled PMOS transistors coupled to the digit lines. The sources of the NMOS transistors are coupled to a common node, which during operation receives an NMOS activation signal RNL_. Similarly, the sources of the PMOS transistors are also coupled to a common node that receives a complementary activation signal ACT. The RNL— signal is typically provided by ground or a negative supply voltage and the ACT signal is typically provided by a power supply voltage. When a memory cell is accessed, the voltage of one of the digit lines increases or decreases slightly, depending on whether the memory cell coupled to the digit line is charged or not, resulting in a voltage differential between the digit lines. While the voltage of one digit line increases or decreases slightly, the other digit line does not and serves as a reference for the sensing operation. Respective transistors are enabled due to the voltage differential, thereby coupling the slightly higher voltage digit line to the ACT node and the other digit line to the RNL— node to further drive each of the digit lines in opposite directions and amplify the selected digit line signal.
The digit lines are equilibrated during a precharge period, such as to Vcc/2, so that a voltage differential can be accurately detected during a subsequent sensing operation. However, due to random threshold voltage mismatch of transistor components, the digit lines may be abruptly imbalanced before a voltage change is detected on one of the digit lines. Such threshold voltage deviations can cause the sense amplifier to erroneously amplify input signals in the wrong direction. A portion of a prior art threshold voltage compensated sense amplifier 100 is shown in FIG. 1. The sense amplifier 100 is shown with complimentary digit lines D and D— coupled to sense nodes 112, 114, respectively. Capacitors 110 are coupled to respective digit lines D and D— to represent digit line capacitance. The sense amplifier 100 additionally includes a pair of cross-coupled NMOS transistors 116, 118 whose source terminals are coupled to receive an RNL— activation signal at a common node. The gates of the transistors 116, 118 are coupled to respective drain terminals through switches 120A,B in a diode configuration. The drain terminals of the transistors 116, 118 are additionally coupled to sense nodes 112, 114 through respective switches 121A, B.
During the precharge period, the switches 120A,B are initially disabled and the switches 121A,B are enabled to place the sense amplifier 100 in a normal cross-coupled (latch) configuration, and the sense nodes 112, 114 and the RNL— node are initially precharged and equilibrated to Vcc/2. While in this compensation period, the RNL— node is next coupled to ground and the switches 120A,B are enabled while the switches 121A,B are disabled to place the transistors 116, 118 in a diode-coupled configuration. The voltage at sense node 112, which is cross-coupled to the gate and drain of the transistor 118 is set to a voltage equal to a threshold voltage VTN0 of the transistor 118, since the voltage across the transistor 118 is equal to its threshold voltage. Similarly, the voltage at sense node 114 is set to a voltage equal to a threshold voltage VTN1 of the transistor 116. The switches 120A,B are then disabled and the switches 121A,B are enabled such that the transistors 116, 118 are again placed in a normal latch configuration before the sensing operation begins. Therefore, any offset due to mismatches in transistor parameters of the transistors 116, 118 are compensated for by the voltage differential between sense nodes 112, 114 before sensing occurs.
Although the prior art sense amplifier 100 reduces threshold voltage mismatches between the NMOS transistors 116, 118, the switches 121A,B which are directly in the sensing path between the sense nodes 112, 114 and the transistors 116, 118, can negatively affect performance due to mismatches between the switches 121A,B. That is, by placing additional components on the sensing path may cause further digit line offsets as a result of mismatched switch components 120A,B. Additionally, the switches 121A,B may reduce sensing gain of the sense amplifier 100.
There is, therefore, a need for an alternative sense amplifier design that reduces threshold voltage mismatches.